4-megabit?2.5-volt?or?2.7-volt?DataFlash?AT45DB041BFor?New?Designs?Use?AT45DB041DThe?DataFlash?incorporates?an?internal?address?counter?that?will?automaticallyincrement?on?every?clock?cycle,?allowing?one?continuous?read?operation?without?the?need?ofadditional?address?sequences.?To?perform?a?continuous?read,?an?opcode?of?68H?or?E8H?must?beclocked?into?the?device?followed?by?24?address?bits?and?32?don’t?care?bits.?The?first?four?bits?ofthe?24-bit?address?sequence?are?reserved?for?upward?and?downward?compatibility?to?larger?andsmaller?density?devices?(see?Notes?under?“Command?Sequence?for?Read/Write?Operations”?diagram).The?next?11?address?bits?(PA10?-?PA0)?specify?which?page?of?the?main?memory?array?toread,?and?the?last?nine?bits?(BA8?-?BA0)?of?the?24-bit?address?sequence?specify?the?starting?byteaddress?within?the?page.?The?32?don’t?care?bits?that?follow?the?24?address?bits?are?needed?to?initialize?the?read?operation.?Following?the?32?don’t?care?bits,?additional?clock?pulses?on?the?SCKpin?will?result?in?serial?data?being?output?on?the?SO?(serial?output)?pin.A?low-to-high?transition?on?the?CS?pin?will?terminate?the?read?operation?and?tri-state?the?SO?pin.The?maximum?SCK?frequency?allowable?for?the?Continuous?Array?Read?is?defined?by?the?fCARspecification.?The?Continuous?Array?Read?bypasses?both?data?buffers?and?leaves?the?contentsof?the?buffers?unchanged.5.1.2?Main?Memory?Page?ReadA?Main?Memory?Page?Read?allows?the?user?to?read?data?directly?from?any?one?of?the?2048?pagesin?the?main?memory,?bypassing?both?of?the?data?buffers?and?leaving?the?contents?of?the?buffersunchanged.?To?start?a?page?read,?an?opcode?of?52H?or?D2H?must?be?clocked?into?the?device?followed?by?24?address?bits?and?32?don’t?care?bits.?The?first?four?bits?of?the?24-bit?addresssequence?are?reserved?bits,?the?next?11?address?bits?(PA10?-?PA0)?specify?the?page?address,and?the?next?nine?address?bits?(BA8?-?BA0)?specify?the?starting?byte?address?within?the?page.The?32?don’t?care?bits?which?follow?the?24?address?bits?are?sent?to?initialize?the?read?operation.Following?the?32?don’t?care?bits,?additional?pulses?on?SCK?result?in?serial?data?being?output?onthe?SO?(serial?output)?pin.?The?CS?pin?must?remain?low?during?the?loading?of?the?opcode,?theaddress?bits,?the?don’t?care?bits,?and?the?reading?of?data.?When?the?end?of?a?page?in?main?memory?is?reached?during?a?Main?Memory?Page?Read,?the?device?will?continue?reading?at?thebeginning?of?the?same?page.?A?low-to-high?transition?on?the?CS?pin?will?terminate?the?read?operation?and?tri-state?the?SO?pin.Pin?Name?FunctionCS?Chip?SelectSCK?Serial?ClockSI?Serial?InputSO?Serial?OutputWP?Hardware?Page?Write?Protect?PinBuffer?ReadData?can?be?read?from?either?one?of?the?two?buffers,?using?different?opcodes?to?specify?whichbuffer?to?read?from.?An?opcode?of?54H?or?D4H?is?used?to?read?data?from?buffer?1,?and?an?opcodeof?56H?or?D6H?is?used?to?read?data?from?buffer?2.?To?perform?a?Buffer?Read,?the?eight?bits?of?theopcode?must?be?followed?by?15?don’t?care?bits,?nine?address?bits,?and?eight?don’t?care?bits.?Sincethe?buffer?size?is?264?bytes,?nine?address?bits?(BFA8?-?BFA0)?are?required?to?specify?the?first?byteof?data?to?be?read?from?the?buffer.?The?CS?pin?must?remain?low?during?the?loading?of?the?opcode,the?address?bits,?the?don’t?care?bits,?and?the?reading?of?data.?When?the?end?of?a?buffer?isreached,?the?device?will?continue?reading?back?at?the?beginning?of?the?buffer.?A?low-to-high?transition?on?the?CS?pin?will?terminate?the?read?operation?and?tri-state?the?SO?pin.Status?Register?ReadThe?status?register?can?be?used?to?determine?the?device’s?Ready/Busy?status,?the?result?of?aMain?Memory?Page?to?Buffer?Compare?operation,?or?the?device?density.?To?read?the?status?register,?an?opcode?of?57H?or?D7H?must?be?loaded?into?the?device.?After?the?last?bit?of?the?opcode?isshifted?in,?the?eight?bits?of?the?status?register,?starting?with?the?MSB?(bit?7),?will?be?shifted?out?onthe?SO?pin?during?the?next?eight?clock?cycles.?The?five?most?significant?bits?of?the?status?registerwill?contain?device?information,?while?the?remaining?three?least-significant?bits?are?reserved?forfuture?use?and?will?have?undefined?values.?After?bit?0?of?the?status?register?has?been?shifted?out,the?sequence?will?repeat?itself?(as?long?as?CS?remains?low?and?SCK?is?being?toggled)?startingagain?with?bit?7.?The?data?in?the?status?register?is?constantly?updated,?so?each?repeatingsequence?will?output?new?data.

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